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1 low input voltage and high efficiency synchronous boost converter with 1.3a switch isl78113a the isl78113a provides a tiny and convenient boost power supply solution to generate a regulated output up to 500ma from any sub-5v secondary rail found in an automotive electrical system, including battery powered applications (nicd, nimh, or one-cell li-ion /li-polymer). it offers an adjustable output (3.0v to 5.2v ) supporting usb-otg or hdmi applications. the device is ab le to supply 500ma from a 3v input and 5v output, and has a typical 1.3a peak current limit. the isl78113a is a fully integr ated, internally compensated, synchronous converter optimized to maximize efficiency and reduce the overall solution size and bill of materials. its high 2mhz switching frequency allows the use of tiny, low-profile inductors and chip capacitors. it also eliminates potential interference within the am radio band and the external emi filtering needed for converters switching at lower rates. to minimize power consumption while off, the device features an ultra-low current shutdown mode dropping quiescent current to 50na typical. isl78113a is supplied in an 8 ld dfn package. the device is rated to operate over the temperature range of -40c to +105c. features ? output disconnect during sh utdown preventing output precharging and uncontrolled short-circuit current ? input voltage range: 0.8v to 4.7v ? output current: up to 500ma (v bat = 3v, v out = 5v) ?logic control shutdown (i q < 1a) ? 2mhz switching frequency ? up to 95% efficiency at ty pical operating conditions ? fault protection: ovp, ocp, otp, uvlo ? 2mmx2mm 8 ld dfn package ? qualified for automotive operations applications ? automotive head units and infotainment systems: especially those including portable hdmi and usb-otg connectivity ? automotive camera systems figure 1. typical application figur e 2. efficiency vs load current sw en gnd fb v out v bat 7 2 4 5 1 8 6.8 h 10f 10f v bat = 0.8v to 4.7v v out = 422 80.6 5.0v/500ma isl78113aaraz ? ? 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 load current i load (a) efficiency (%) v bat = 4.2v v bat = 3.4v v bat = 3v v bat = 2.3v v bat = 3.6v caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. may 1, 2014 fn8638.0
isl78113a 2 fn8638.0 may 1, 2014 submit document feedback block diagram gate driver and anti-cross conduction 2mhz oscillator g m voltage clamp n-well switch voltage selector uvlo thermal shutdown digital soft-start reference generator control logic and fault monitoring ovp current sense start-up en v out fb current limit sw v out sw zcd v bat v out v int v int off on c1 c2 l1 r1 r2 8 2 7 5 1 4 slope comp 6
isl78113a 3 fn8638.0 may 1, 2014 submit document feedback pin configuration isl78113a adjustable output (8 ld dfn) top view 1 2 3 4 5 6 7 8 pgnd v out nc fb en agnd v bat sw pin descriptions pin numbers symbol pin description 1pgndpower ground. 2v out device output. 3 nc no connection. 4 fb feedback pin of the converter. connect voltage divider resistors between v out , fb and gnd for desired output. 5 en the en pin is an active-high logic input for enabling the de vice. when asserted high, the bo ost function begins. when driven low, the device is completely disabled, and current is blocked from flowing from the sw pin to the output and vice versa. this pin may be tied either high to enable the device or low to disable. 6 agnd analog ground. 7v bat device input supply from a battery. connect a 1 0f ceramic capacitor from vbat to power ground. 8 sw the sw pin is the switching node of the power converter. conn ect one terminal of the inductor to the sw pin and the other to power input. epad the exposed pad must be connected to pgnd pin for proper elec trical performance. place as many vias as possible under the pad connecting to the system gnd plane for optimal thermal performance. ordering information part number (notes 1, 2, 3) part marking v out (v) temp range (c) package (pb-free) pkg. dwg. # ISL78113AARAZ-T aar adjustable -40 to +105 8 ld dfn l8.2x2d notes: 1. use ?-t7a? suffix for 250 pieces tape and reel. please refer to tech brief tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl78113a . for more information on msl please see tech brief tb363 .
isl78113a 4 fn8638.0 may 1, 2014 submit document feedback absolute maximum rating s thermal information v bat , en, v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v sw voltage dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6.5v pulse <10ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 8.0v esd ratings human body model (tested per aec-q100-002) . . . . . . . . . . . . . . . . 4kv machine model (tested per aec-q100-003) . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per aec-q100-011). . . . . . . . . . . . .2.2kv latch up (tested per aec-q100-004; class ii, level a) . . . . . . . . . . . 15ma thermal resistance (typical) t ja (c/w) t jc (c/w) 8 ld dfn package (notes 4, 5). . . . . . . . . . 80 15 maximum junction temperature (plastic package). . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tb493 recommended operating conditions v bat (after start-up) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8v to 4.7v v out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v bat + 0.2v) to 5.2v operating junction temperature range . . . . . . . . . . . . . .-40c to +125c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +105c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. t ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for t jc the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications v bat = 3.0v, v out = 5v, l = 4.7h, t a = +25c. boldface limits apply over the operating temperature range, -40c to +105c . parameter symbol test conditions min (note 6) typ max (note 6) units start-up voltage v min v en = 1.2v, r load = 50 0.6 0.75 0.9 v input undervoltage lockout v uvlo v en = v bat, r load = 50 0.66 0.70 0.76 v feedback voltage v fb 784 800 816 mv output voltage v bat = 2v 3.0 5.2 v feedback pin input current -100 100 na quiescent current from v out i q1 v bat = v en = 1.2v, no load (note 7) 5.5 10 ma shutdown current from v bat i sd v en = 0v, v bat = 1.2v, v o = 0 0.05 2.8 15 1 1.3 1.6 a maximum duty cycle d max 82 87.5 % pwm switching frequency f osc 1.73 2 2.23 mhz en logic high 2.5v < v bat < 4.7v 1.2 v v bat < 2.5v 0.48*v bat v en logic low 2.5v < v bat < 4.7v 0.35 v v bat < 2.5v 0.14*v bat v soft start-up time c out = 4.7 1 ms load regulation -0.5 0.01 0.5 % line regulation v bat = 3.0v to 3.6v, i load = 1ma -0.5 0.03 0.5 % minimum sw low in pwm mode t min(on) 42 49 ns output overvoltage protection threshold 5.9 v thermal shutdown t sd 150 o c thermal shutdown hysteresis 25 o c notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 7. i q1 is measured at v out and multiplied by v out /v bat ; thus, the equivalent input quiescent current is calculated.
isl78113a 5 fn8638.0 may 1, 2014 submit document feedback detailed description current mode pwm operation the control scheme of the device is based on the peak current mode control and the control loop is compensated internally. the peak current of the n-channel mosfet switch is sensed to limit the maximum current flowing through the switch and the inductor. the typical current limit is set to 1.3a. the control circuit includes a current ramp generator, slope compensator, error amplifier an d a pwm comparator (see the ?block diagram? on page 2). the ramp signal is derived from the inductor current. this ramp signal is then compared to the error amplifier output to generate th e pwm gating signals for driving both n-channel and p-channel mo sfets. the pwm operation is initialized by the clock from the internal oscillator (typical 2mhz). the n-channel mosfet is turned on at the beginning of a pwm cycle, the p-channel mosfet rema ins off, and the current starts ramping up. when the sum of the ramp and the slope compensator output reaches the error amplifier output voltage, the pwm comparator outputs a sign al to turn off the n-channel mosfet. here, both mosfets rema in off during the dead-time interval. next, the p-channel mosfet is turned on and remains on until the end of this pwm cycle. during this time, the inductor current ramps down until the next cl ock. at this point, following a short dead time, the n-channel mosfet is again turned on, repeating as previously described. synchronous rectifier the isl78113a integrates one n-channel mosfet and one p-channel mosfet to realize a synchronous boost converter. because the commonly used discrete schottky rectifier is replaced with the low r ds(on) p-channel mosfet, the power conversion efficiency reaches a value above 90%. v out isolation since a typical step-up converter has a conduction path from the input to the output via the body diode of the p-channel mosfet, a special circuit (see the ?block diagram? on page 2) is used to reverse the polarity of the p-cha nnel body diode when the device is shut down. thus, this configuration completely disconnects the load from the input during shutdown of the converter. the benefit of this feature is that the batter y will not be completely depleted during shutdown of the converter. no additional components are needed to disconnect the battery from the output of the converter. soft-start the soft start-up duration is the time between the device being enabled and v out rising to within 3% of the target voltage. when the device is enabled, the start-up cycle starts with a linear operating phase. during the linear phase, the rectifying switch is turned on in a current limited configuration, delivering about 350ma, until the output capacitor is charged to approximately 90% of the input voltage. at this point, pwm operation begins in boost mode. if the output voltage is below 2.3v, pwm switching is done at a fixed duty-cycle of 75% until the output voltage reaches 2.3v. when the output voltage exceeds 2.3v, the closed-loop current mode pwm loop overrides the duty cycle until the output voltage is regulated. peak inductor current is ramped to the current limit value (typical ly 1.3a) during the soft-start period to limit in-rush current from the input source. fault monitoring begins approximately 2ms after the device is enabled. to start up with a slow v bat ramp-up rate is likely to cause the device to enter hiccup mode. this is a result of the input voltage dropping due to start-up current, which causes a fault of v out out of regulation, especial ly at high load and cold temperature. check the input ramp-up rate and a faster input slew rate would help to resolve this. over-temperature protection (otp) the device offers over-temperature protection. a temperature sensor circuit is integrated and monitors the internal ic temperature. once the temperature exceeds the preset threshold (typically +150c), the ic shuts down immediately. the otp has a typical hysteresis of +25c. when the device temperature decreases by this, the device starts operating.
isl78113a 6 fn8638.0 may 1, 2014 submit document feedback fault monitoring fault monitoring starts 2ms after start-up. table 1 shows the response to different detected faults. printed circuit board layout recommendations the isl78113a is a high frequency switching boost converter. accordingly, the converter has fast voltage change and high switching current that may cause emi and stability issues if the layout is not done properly. therefore, careful layout is critical to minimize the trace inductance an d reduce the area of the power loop. power components such as input capacitor, inductor, and the output capacitors should be placed as close to the device as possible. board traces that carry high switching current should be routed wide and short. a solid power ground plane is important for emi suppression. the switching node (sw pin) of the converter and the traces connected to this pin are very noisy. noise sensitive traces such as the fb trace should be kept away from the sw node. the voltage divider should be placed close to the fb pin to prevent noise pickup. figure 3 shows the recommended pcb layout. in the 8 ld dfn package, the heat generated in the device is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. it is recommended to add at least 4 vias within the pad to the gnd plane for the best thermal dissipation. output voltage setting resistor selection for isl78113a, resistors r 1 and r 2 , shown in the ?block diagram? on page 2, set the desired output voltage values. the output voltage can be calculated using equation 1: where v fb is the internal fb reference voltage (0.8v typical). the current flowing through the divider resistors is calculated as v out /(r 1 + r 2 ). the resistance is chosen based on the minimum expected load for v out and the minimum pwm on time (pwm low; 42ns typical). this will provide a small constant current that limits the v out and voltage in light load conditions. r 1 and r 2 should be placed close to the fb pin of the device to prevent noise pickup. table 1. fault detection and response fault condition detection details action low battery voltage v bat < 0.7v shutdown until v en or v bat is cycled. v out out of regulation v out is 10% below the target output voltage. shutdown only if v bat and v out fall below 2.1v. device automatically restarts after 200ms. short circuit v out falls below v bat . shutdown immediately. device automatically restarts after 200ms. over-temperature protection die temperature is > +150c. switching st ops. device automatically restarts when temperature decrease s to +125c. output overvoltage protection v out > 5.9v switching stops until en pin is toggled or power is cycled. figure 3. recommended pcb layout v out v fb 1 r 1 r 2 ------ - + ?1 ? x = (eq. 1)
isl78113a 7 fn8638.0 may 1, 2014 submit document feedback inductor selection an inductor with core material suitable for high frequency applications (e.g., ferrite) is desirable to minimize core loss and improve efficiency. the inductor should have a low dcr to reduce copper loss. moreover, the inductor saturation current should be higher than the maximum peak current of the device; i.e., 1.6a. the device is designed to operate with an inductor value of 2.2h to 6.8h to provide stable operation across the range of load, input and output voltages. table 2 shows recommended inductors. capacitor selection input capacitor a minimum of a 10f ceramic capacitor is recommended to provide stable operation under ty pical operating conditions. for input voltage less than 1.0v application, an additional 2.2f ceramic capacitor is recommended for better noise filtering and emi suppression. the input capacito r should be placed close to the input pin, gnd pin, and the non-switching terminal of the inductor. output capacitor for the output capacitor, a ceramic capacitor with small esr is recommended to minimize output voltage ripple. a typical 10f should be used to provide stable operation at different typical operating conditions. the output capacitor should be placed close to the output pin and gnd pin of the device. table 3 shows the recommended capacitors. forced pwm operation the part has forced pwm operation. during a no-load condition the low-side fet is forced on for a short pulse with minimum on-time (42ns typical) in every cycle and does not allow for pulse skipping. the part is also implemented with diode emulation mode to turn off the upper side mosfet when inductor current drops to 0 and prevents any negative inductor current. therefore in no load to light load (less than several ma) conditions, the output voltage is pushed higher than regulation point, which may be out of the user?s output voltage specifications. this issue can be resolved by addi ng a small load (several ma) to keep the output in regulation. the procedure to calculate the minimum load required due to these forced pwm pulses is elaborated in the following. figure 4 shows the inductor waveform in the forced pwm operation at no load. t min(on)_lfet is the time the low-side mosfet is forced on. during t min(on) time, inductor current is charged with slew rate of v in /l. the peak inductor current at the end of t min(on) can be calculated in equation 2. after t min(on) time, low-side mosfet is turned off, inductor current is free-wheeling throug h the high-side mosfet from v in to v out until the inductor current ramps down to 0 and the high-side mosfet is turned off. the duration of this free-wheeling period (t fw ) can be calculated in equation 3. during this free-wheeling period, the charge to the output is shown as q in figure 4 on page 8, which can be calculated as shown by equation 4. the isl78113a outputs charge of q to the output every switching cycle, therefore the average current to due to the t min(on) pulses can be calculated as shown by equation 5. where f sw is the switching frequency. summarizing from equations 2 through 5, the average current charged to the output due to the t min(on) pulses can be calculated by equation 6. table 2. inductor vendor information manufacturer series website wrth elektronik we-tpc, type s www.we-online.com table 3. capacitor vendor information manufacturer series website avx x7r www.avx.com murata x7r www.murata.com taiyo yuden x7r www.t-yuden.com tdk x7r www.tdk.com il peak v in t min on x l ---------------------------------------- = (eq. 2) t fw il peak l x v out v in ? ------------------------------- - = (eq. 3) q0.5il peak t fw x x = (eq. 4) i out avg qf sw x = (eq. 5) i out avg 0.5 f sw x v in t min on x 2 x lv out v in ? x --------------------------------------------------------------------------------- = (eq. 6)
isl78113a 8 fn8638.0 may 1, 2014 submit document feedback minimum load required in forced pwm mode in a no load condition, in order to maintain the output voltage in regulation, a small load has to be added in the output to absorb the output current due to forced pwm pulses. equation 6 can be used to calculate the minimum required load in worst cases. the worst cases refer to f sw , v in , t min(on) , l, v out in equation 6. ? use the maximum v in for the worst case. ? specify the allowed maximum vout voltage v in(max) and use it in the worst case calculation, basi cally the target is to have the minimum load keeping the v out below the maximum acceptable voltage. ? use the maximum switching fr equency of 2.23mhz specified in the ?electrical specificatio ns? table on page 4. maximum frequency is the worst case since it delivered most pulses with fixed charges to the output. ? use the minimum inductor value considering inductance variations (normally -20% of no minal value). for the inductor selection, note the higher the inductance, the less the required minimum load. ? use the maximum t min(on) time of 49ns specified in the ?electrical specifications? table on page 4. maximum t min(on) time is the worst case since it cause higher inductor peak current and higher charge to the output. an example of the typical conditions are listed as follows: ?v in typ = 3v ?v out typ = 5v ?f sw typ = 2mhz ?l nominal = 6.8h to calculate the minimum required load, the worst conditions we can use are, ?v in(max) = 3.6v (specified in customer system) ?v out(max) = 5.25v (specified in customer system) ?f sw = 2.23mhz ?l min = (-20%) l nominal = 5.44h using the above worst case parameters in equation 6, the calculated output current (i out(avg) ) is 3.87ma, which is the minimum required load to be added in the output to absorb the output current due to forced pwm pulses. extra margin can be added depending on the system worst case condition. figure 4. average output current due to fo rced pwm pulses at no load condition q sr = (v out - v in ) sr = v in /l il t min(on) t fw q 1/f sw il peak = v in /l* t min(on) q = 0.5 * il peak * t fw i out(avg ) = q*f sw t fw = il peak * l/( vout - v in ) i out(avg ) = 0.5 * ( v in /l* t min(on) ) 2 *l/(v out - v in ) * f sw
isl78113a 9 fn8638.0 may 1, 2014 submit document feedback typical characteristics v in = 3.4v, v out = 5v, l = 6.8h, c out = 10f, r 1 = 422
isl78113a 10 fn8638.0 may 1, 2014 submit document feedback figure 11. start-up after enable (i load = 250ma) figure 12. start-up after enable (i load = 50ma) figure 13. load transient response (20ma to 150ma) figure 14. load transient response (20ma to 250ma) figure 15. load transient response (1 00ma to 500ma) figure 16. load regulation typical characteristics v in = 3.4v, v out = 5v, l = 6.8h, c out = 10f, r 1 = 422
isl78113a 11 intersil automotive qualified products are manufactured, asse mbled and tested utilizing ts16949 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8638.0 may 1, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support figure 17. efficiency vs load current typical characteristics v in = 3.4v, v out = 5v, l = 6.8h, c out = 10f, r 1 = 422 revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change may 1, 2014 fn8638.0 initial release.
isl78113a 12 fn8638.0 may 1, 2014 submit document feedback package outline drawing l8.2x2d 8 lead dual flat no-lead plastic package (dfn) with exposed pad rev 0, 3/11 bottom view detail "x" side view typical recommended land pattern top view pin #1 b 0.10 m a c c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c index area pin 1 6 (4x) 0.15 a b 1 package 2.00 2.00 1.550.10 0.900.10 0.22 ( 6x0.50 ) ( 8x0.22 ) 2.00 2.00 ( 8x0.30 ) ( 8x0.20 ) ( 8x0.30 ) 0.50 8 0.90 1.55 6x 0.900.10 index area outline located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6 4

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